Magnetoelectronic devices, spin electronic devices, and spintronic devices are synonymous terms for devices that make use of effects predominantly caused by electron spin. Magnetoelectronics are used in numerous information devices to provide non-volatile, reliable, radiation resistant, and high-density data storage and retrieval. The numerous magnetoelectronic information devices include, but are not limited to, Magnetoresistive Random Access Memory (MRAM), magnetic sensors, and read/write heads for disk drives.
Typically an MRAM includes an array of magnetoresistive memory elements. Each magnetoresistive memory element typically has a structure that includes multiple magnetic layers separated by various non-magnetic layers, such as a magnetic tunnel junction (MTJ), and exhibits an electrical resistance that depends on the magnetic state of the device. Information is stored as directions of magnetization vectors in the magnetic layers. Magnetization vectors in one magnetic layer are magnetically fixed or pinned, while the magnetization direction of another magnetic layer may be free to switch between the same and opposite directions that are called “parallel” and “antiparallel” states, respectively. Corresponding to the parallel and antiparallel magnetic states, the magnetic memory element has low and high electrical resistance states, respectively. Accordingly, a detection of the resistance allows a magnetoresistive memory element, such as an MTJ device, to provide information stored in the magnetic memory element. There are two completely different methods used to program the free layer: field switching and spin-torque switching. In field-switched MRAM, current carrying lines adjacent to the MTJ bit are used to generate magnetic fields that act on the free layer. In spin-torque MRAM, switching is accomplished with a current pulse through the MTJ itself. The angular momentum carried by the spin-polarized tunneling current causes reversal of the free layer, with the final state (parallel or antiparallel) determined by the polarity of the current pulse. Spin-torque transfer is known to occur in MTJ devices and giant magnetoresistance devices that are patterned or otherwise arranged so that the current flows substantially perpendicular to the interfaces, and in simple wire-like structures when the current flows substantially perpendicular to a domain wall. Any such structure that exhibits magnetoresistance has the potential to be a spin-torque magnetoresistive memory element. In some device designs the free magnetic layer of the MTJ may have stable magnetic states with magnetization in the film plane, and in other cases the stable states have magnetization perpendicular to the plane. In-plane devices typically have their magnetic easy axis defined by the in-plane shape of the free layer and perpendicular devices typically employ materials with a perpendicular magnetic anisotropy (PMA) that create a perpendicular easy axis.
Spin-torque MRAM (ST-MRAM), also known as spin-torque-transfer RAM (STT-RAM), is an emerging memory technology with the potential for non-volatility with unlimited endurance and fast write speeds at much higher density than field-switched MRAM. Since ST-MRAM switching current requirements reduce with decreasing MTJ dimensions, ST-MRAM has the potential to scale nicely at even the most advanced technology nodes. However, the number of metal connect lines (bit lines, word line, etc.) can limit the scalability of ST-MRAM.
All known ST-MRAM bitcell layouts that support bi-directional current use one bitline per column connected to each memory element and a separate current path, parallel to the bitline, connected to the source of select transistors, each select transistor connected to the other end of each memory element, the source lines and bitlines driven to a voltage level by circuitry outside of the memory array. Known devices typically connect to the top of the MTJ on an upper level metal while connecting to the select transistor on a lower level metal. Use of the lower source line typically requires >20f2 area in a standard CMOS process, due to the area required for the source line along with the area required for the connection up from the select device to the bottom of the MTJ.
Accordingly, it is desirable to provide ST-MRAM structures that provide a simplified fabrication process and structure by reducing the number of source lines and bitlines accessible to circuitry outside of the memory array. Furthermore, other desirable features and characteristics of the exemplary embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.